Apparatus and methods for manufacturing semiconductor structures using protective barrier layer

ABSTRACT

Methods for forming a semiconductor structure including a silicon (Si) containing layer or a silicon germanium (SiGe) layer are provided. The methods include depositing a protective barrier (e.g., liner) layer over the semiconductor structure, forming a flowable dielectric layer over the liner layer, and exposing the flowable dielectric layer to high pressure steam. A cluster system includes a first deposition chamber configured to form a semiconductor structure, a second deposition chamber configured to perform a liner deposition process to form a liner layer, a third deposition chamber configured to form a flowable dielectric layer over the liner layer, an annealing chamber configured to expose the flowable oxide layer to high pressure steam.

BACKGROUND Field

Implementations of the present disclosure generally relate to methods and apparatus for manufacturing semiconductor structures using a protective barrier (e.g., liner) layer.

Description of the Related Art

Widths of trenches formed in semiconductor devices have been narrowed to a point where an aspect ratio of trench depth to trench width becomes high enough to make it challenging to fill the trench with dielectric material. Flowable dielectric material, such as silicon oxide (SiOx), deposited at low temperature and annealed under high pressure steam can fill high-aspect-ratio trenches with quality oxide material without forming any seams or voids. However, any underlying material exposed to the steam, such as silicon (Si), can be converted into an oxide material, affecting quality of underlying layers. A thickness of the converted oxide can be several angstroms (Å). For example, silicon germanium (SiGe) materials may be particularly susceptible to oxidation when exposed to high pressure steam.

Thus, there is a need in the art for a fabrication method and apparatus to address the above-mentioned issues.

SUMMARY

Implementations of the present disclosure generally relate to methods and apparatus for manufacturing semiconductors using a protective barrier (e.g., liner) layer.

In one embodiment, a method for processing a substrate is provided. The method includes forming a semiconductor structure on a substrate wherein the semiconductor structure includes a silicon (Si) containing layer or a silicon germanium (SiGe) layer. The method also includes performing a liner deposition process to form a liner layer over the semiconductor structure. The method also includes performing a flowable layer deposition process to deposit a flowable layer over the liner layer. The method also includes performing an annealing process by exposing a surface of the flowable layer to high pressure steam, wherein the liner layer prevents oxidation of the underlying Si containing layer or SiGe layer during the annealing process, at least a portion of the liner layer is gradually reduced by oxidation during the annealing process.

In another embodiment, a cluster system capable of processing a substrate is provided. The cluster system includes a first deposition chamber configured to form a semiconductor structure on a substrate, wherein the semiconductor structure includes a silicon (Si) containing layer or a silicon germanium (SiGe) layer. A second deposition chamber is configured to form a liner layer over the semiconductor structure. A third deposition chamber is configured to form a flowable layer over the liner layer. An annealing chamber is configured to perform an annealing process by exposing the flowable oxide layer to high pressure steam, wherein the liner layer prevents oxidation of the underlying Si containing layer or SiGe layer during the annealing process. At least a portion of the liner layer is gradually reduced by oxidation during the annealing process.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical implementations of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.

FIG. 1 illustrates a flowchart showing a fabrication process for forming a flowable dielectric layer over a semiconductor structure according to an embodiment of the disclosure.

FIGS. 2A to 2E illustrate schematic, cross-sectional views of a portion of a semiconductor structure after each fabrication operation of FIG. 1 is performed according to an embodiment of the disclosure.

FIG. 3 illustrates schematic, cross-sectional views of semiconductor structures with various combinations of layers deposited thereon after an annealing process is performed according to an embodiment of the disclosure.

FIG. 4 is a schematic top view of a processing system that can be used to perform the fabrication processes described with respect to FIG. 1, according to an embodiment of the present disclosure.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one implementation may be beneficially utilized in other implementations without specific recitation.

DETAILED DESCRIPTION

Implementations of the present disclosure generally relate to methods and apparatus for manufacturing semiconductor structures using a protective barrier (e.g., liner) layer. In particular, methods presented herein include forming a semiconductor structure including a silicon (Si) containing layer or a silicon germanium (SiGe) layer, depositing a liner layer over the semiconductor structure, forming a flowable layer over the liner layer, and exposing the flowable layer to high pressure steam, wherein the liner layer prevents oxidation of the underlying Si containing layer or a SiGe layer during the annealing process, and at least a portion of the liner layer is gradually reduced by oxidation during the annealing process.

FIG. 1 illustrates a flowchart showing a fabrication process 100 for forming a flowable dielectric layer over a semiconductor structure according to an embodiment of the disclosure. The fabrication process 100 may be part of a multi-operation fabrication process of a semiconductor device, for example, including a planar structure, a fin field effect transistor (FinFET) structure or a horizontal gate-all-around (hGAA) structure. Each operation of the fabrication process 100 may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing specified logical function(s). In some implementations, the operations of the fabrication process may occur simultaneously, substantially concurrently, or in an order other than that illustrated in FIG. 1. Each operation and combinations of operations of the fabrication process 100 can be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The fabrication process begins at operation 102 where a semiconductor structure is formed on a substrate. The semiconductor structure includes one or more layers of a silicon-containing material, such as silicon (Si) material or a silicon germanium (SiGe) containing material. The Si containing layer or SiGe layer can be epitaxially grown over a surface of the substrate.

The substrate may be any substrate capable of having material deposited thereon, such as a silicon substrate, for example silicon (doped or undoped), crystalline silicon, silicon oxide, doped or undoped polysilicon, or the like, a germanium substrate, a silicon germanium (SiGe) substrate, a Ill-V compound substrate, such as a gallium arsenide substrate, a silicon carbide (SiC) substrate, a patterned or non-patterned semiconductor-on-insulator (SOI) substrate, a carbon doped oxide, a silicon nitride, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, a solar array, solar panel, a light emitting diode (LED) substrate, glass, sapphire, or any other materials such as metals, metal alloys, and other conductive materials. One or more electrical devices such as various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like, could be formed in the substrate. It is contemplated that the substrate is not limited to any particular size or shape. For example, the substrate may be a circular substrate having a 200 mm diameter, a 300 mm diameter, or other diameters, such as 450 mm, among others. The substrate may also be any polygonal, square, rectangular, curved, or otherwise non-circular workpiece.

At operation 104, the semiconductor structure is patterned and etched to form a feature on the substrate, such as a trench or a gap. For example, the semiconductor structure may be patterned in a lithography system and etched in an etch chamber. In one embodiment, a photolithography processes, such as extreme ultraviolet patterning processes, may be utilized to process the semiconductor structure. In one embodiment, an aspect ratio of the trench or gap etched into the semiconductor structure is about 1:1, about 2:1, about 3:1, about 5:1, about 10:1, about 15:1, about 20:1, about 30:1, about 50:1, about 100:1, or greater.

In one embodiment, the aspect ratio of the trench or gap is between about 10:1 and about 30:1, for example about 15:1. The term “aspect ratio” refers to the ratio of the height dimension to the width dimension of a particular feature, for example, the trench or gap formed in the substrate.

At operation 106, a protective barrier (e.g., a liner) layer is formed on sidewalls of the semiconductor structure while the substrate is positioned in a deposition chamber. In one embodiment, the liner layer is deposited, for example, by chemical vapor deposition, atomic layer deposition, or epitaxial deposition. In another embodiment, the liner layer is formed (i.e., grown) by suitable processes, such as a thermal oxidation process or a thermal nitridation process. The liner layer prevents oxidation of an underlying layer of the semiconductor structure or substrate (e.g., a Si-containing layer or SiGe layer) during deposition of a flowable dielectric layer deposition and during an annealing process.

In one embodiment, the liner layer can be formed from an oxide material, a nitride material, or an oxynitride based material. For example, the liner material may be a silicon oxide (SiO₂), a silicon nitride (Si₃N₄, also abbreviated SiN), or a silicon oxynitride (SiO_(x)N_(y)) such as SiON or Si₂N₂O. In one embodiment, the oxide material is deposited by a flowable chemical vapor deposition (CVD) process using a deposition chamber. A suitable deposition chamber may include a high-density plasma CVD chamber, a plasma enhanced CVD chamber, a sub-atmospheric CVD chamber, or the like. An example of a suitable apparatus that may be adapted to form the flowable oxide or nitride layer includes the PRODUCER® system or the ULTIMA HDP CVD® system, both available from Applied Materials, Inc., of Santa Clara, Calif. It is contemplated that other suitable deposition chambers, including those from other manufacturers, may also be utilized.

At operation 108, a flowable dielectric layer is formed over the liner layer of the semiconductor structure. The flowable dielectric layer of this disclosure may include any dielectric layer. In one embodiment, the dielectric layer is a silicon-containing layer, which may include, but is not limited to SiC, SiO, SiCN, SiO₂, SiOC, SiOCN, SiON, or SiN. In one example, to form a flowable dielectric layer, a silicon-containing precursor, an oxygen-based radical precursor, and a nitrogen-based radical precursor are introduced into the deposition chamber to form a flowable dielectric layer over the substrate. Additionally or alternatively, the flowable dielectric layer may not contain traceable amount of carbon (i.e., is carbon free or substantially carbon free).

The flowable dielectric layer may be deposited on exposed surfaces of the substrate and into the trenches or gaps formed therein. The flowability of the dielectric layer may be due, at least in part, to the presence of short chained polysilazane polymers in the deposited layer. For example, the deposited layer may have a silazane-type, Si—NH—Si backbone (i.e., a Si—N—H layer). The nitrogen, which allows the formation of short chained polymers and flowability, may originate from either the radical precursors or the silicon-containing precursor. The flowability of the dielectric layer enables the dielectric layer to fill trenches or gaps having high aspect ratios without creating voids in the trenches. Particularly, the flowable dielectric layer fills the trenches in a bottom-up fashion with minimal deposition on the sidewall of the trenches. The flowability of the dielectric layer attenuates as the deposition of the flowable dielectric layer progresses. The flowability of the dielectric layer is removed during a subsequent annealing process.

In one embodiment, suitable silicon-containing precursors include organosilicon compounds having a ratio of oxygen to silicon atoms of about 0 to about 6. Suitable organosilicon compounds may include siloxane compounds, halogenated siloxane compounds that include one or more halogen moieties (e.g., fluoride, chloride, bromide, or iodide), such as tetrachlorosilane, dichlorodiethoxysiloxane, chlorotriethoxysiloxane, hexachlorodisiloxane, and/or octachlorotrisiloxane, and aminosilanes, such as trisilylamine (TSA), hexamethyldisilazane (HMDS), silatrane, tetrakis(dimethylamino)silane, bis(diethylamino)silane, tris(dimethyl-amino)chlorosilane, and methylsilatrane. Other silicon-containing precursors, such as silanes, halogenated silanes, organosilanes, and any combinations thereof, may also be used. Silanes may include silane (SiH4) and higher silanes with the empirical formula SixH (2x+2), such as disilane (Si₂He), trisilane (Si₃a), and tetrasilane (Si₄H₁₀), or other higher order silanes such as polychlorosilane.

The oxygen-based radical precursor may include oxygen radicals that are formed from oxygen (O₂), ozone (O₃), a nitrogen-oxygen compound such as NO, NO₂, or N₂O, a hydrogen-oxygen compound such as water or peroxide, a carbon-oxygen compound such as carbon monoxide or carbon dioxide, and other oxygen-containing precursors, and any combination thereof. The oxygen radicals may be generated remotely and introduced with the silicon-containing precursor. The oxygen-based radical precursor may be activated prior to introduction to the deposition chamber, for example using a remote plasma source, which may have a CCP (capacitively-coupled plasma) or ICP (inductively-coupled plasma) configuration.

The nitrogen-based radical precursor may include nitrogen radicals that are formed from nitrogen (N₂), nitrous oxide (N₂O), nitric oxide (NO), nitrogen dioxide (NO₂), ammonia (NH₃), and any combination thereof. The nitrogen radicals may be generated remotely and introduced with the silicon-containing precursor and the oxygen-based radical precursor. The nitrogen-based radical precursor may be activated prior to introduction to the deposition chamber, for example using a remote plasma source, which may have a CCP (capacitively-coupled plasma) or ICP (inductively-coupled plasma) configuration.

In some implementations, the oxygen-based radical precursor is flowed into the deposition chamber at a first volumetric flowrate and the silicon-containing precursor is flowed into the deposition chamber at a second volumetric flowrate. In one embodiment, a ratio of the first volumetric flowrate to the second volumetric flowrate is between about 0.3:1 and about 0.9:1, such as between about 0.5:1 to about 0.7:1, for example about 0.6:1.

In some implementations, the nitrogen-based radical precursor is flowed into the deposition chamber at a first volumetric flowrate and the silicon-containing precursor is flowed into the deposition chamber at a second volumetric flowrate. In one embodiment, a ratio of the first volumetric flowrate to the second volumetric flowrate is between about 0.2:1 and about 0.8:1, such as between about 0.4:1 to about 0.6:1, for example about 0.5:1.

It is contemplated that the oxygen-based radical precursor or the nitrogen-based radical precursor may be omitted if a radial precursor containing both oxygen and nitrogen radicals is used.

The silicon-containing precursor, the oxygen-based radical precursor, and the nitrogen-based radical precursor can be flowed into a deposition chamber and be reacted at a temperature between about 0 degrees Celsius and about 100 degrees, for example, about 65 degrees Celsius. During formation of the flowable dielectric layer, a pressure of the deposition chamber may be maintained between about 0.1 Torr and about 10 Torr, for example between about 0.5 Torr and about 6 Torr.

At operation 110, the semiconductor structure is subjected to a high pressure annealing process in an annealing chamber. After the annealing process, the flowable dielectric layer exhibits a higher density, better stability, and can withstand higher temperatures. In one embodiment, an optional curing process is performed before the annealing process.

During the high pressure annealing process 110, an annealing gas is introduced into an annealing chamber having the substrate positioned therein. In one embodiment, the annealing gas includes an oxygen component. The annealing gas may also include a hydrogen component. In one embodiment, the annealing gases include one of steam and/or a mixture of steam and oxygen. In one embodiment, the annealing gases further include one of ozone, oxygen, water vapor, heavy water, a peroxide, hydroxide-containing compounds, oxygen isotopes (14, 15, 16, 17, 18, etc.), and non-isotopes of oxygen and/or water. The peroxide may be hydrogen peroxide in a gaseous state. In some embodiments, the annealing gas is an oxidizer that comprises a hydroxide ion, such as but not limited to water vapor or heavy water in vapor form (e.g., steam).

In one example, the annealing gas is dry steam or superheated steam. The dry steam may become superheated steam upon entry into the annealing chamber. The temperature of interior surfaces of the annealing chamber in which the semiconductor structure is processed is maintained to prevent condensation of the annealing gas. For example, the temperature of surfaces of the annealing chamber exposed to the annealing gas is maintained between about 200 degrees Celsius and about 600 degrees Celsius.

During the annealing process, a pressure of the annealing gas within the annealing chamber is maintained between about 1 bar and about 60 bars. For example, the pressure of the processing gas within the annealing chamber is maintained above about 2 bars, such as for example, greater than about 10 bars. In another example, the annealing gas within the annealing chamber is maintained at a pressure between about 10 and about 60 bars, such as between about 20 and about 50 bars. A treat time (e.g., a soak time) of the annealing process 110 may be between about 5 minutes and about 120 minutes, such as between about 30 minutes and about 90 minutes.

FIGS. 2A to 2E illustrate schematic, cross-sectional views of a portion of a semiconductor structure after each fabrication operation is performed according to an embodiment of the disclosure.

FIG. 2A illustrates a schematic, cross-sectional view of a portion of a semiconductor structure 200A after a plurality of layers is deposited over a substrate 202. In one embodiment, the substrate 202 may be a bulk semiconductor substrate in which the substrate comprises a semiconductor material. The bulk semiconductor substrate may comprise any suitable semiconducting material and/or combinations of semiconducting materials for forming a semiconductor structure. In one embodiment, the semiconductor material of the substrate 202 comprises a silicon material. In some embodiments, the semiconductor material of the substrate 202 is a doped material, such as n-doped silicon (n-Si), or p-doped silicon (p-Si).

The semiconductor structure 200A includes a plurality of layers. In one embodiment, the semiconductor structure 200A includes a first layer 204, a second layer 206, and a third layer 208. The second layer 206 may be formed from at least one Ill-V material, such as silicon germanium (SiGe) material. In one example, the second layer 206 has a germanium content of between about 10% and about 50%, such as between about 20% and about 40%. The silicon content of the second layer 206 may be between about 50% and about 90%, such as between about 60% and about 80%. In one embodiment, the second layer 206 is deposited using an epitaxial chemical vapor deposition process.

In one embodiment, the first layer 204 is formed from a silicon containing material, and the third layer 208 is formed from silicon dioxide. In another embodiment, each of the first layer 204, the second layer 206 and the third layer 208 is an SiGe containing layer when the semiconductor structure 200A is fabricated from an SiGe containing material. In yet another embodiment, the first layer 204 and the third layer 208 are formed from any suitable materials, depending on the functions of the semiconductor structures.

FIG. 2B illustrates a schematic, cross-sectional view of a portion of a semiconductor structure 200B. The semiconductor structure 200B illustrated in FIG. 2B corresponds to the semiconductor structure 200A illustrated in FIG. 2A after a patterning process and an etching processes are performed. Both edges of the semiconductor structure 200B have been etched. As a result, a trench or gap can be formed between adjacent semiconductor structures, such as semiconductor structure 200B and an adjacent semiconductor structure.

In one embodiment, photolithography processes, such as extreme ultraviolet patterning processes, may be utilized to etch the semiconductor structure 200A. In another embodiment, self-aligned double or quadruple patterning processes may be utilized to pattern the semiconductor structure 200A.

An example etching process utilized to etch the semiconductor structure 200A is a reactive ion etching (RIE) process. It is contemplated that similar and other etching processes may be utilized. In one embodiment, an RIE process may be performed utilizing a chlorine, bromine, or fluorine based chemistry to anisotropically etch the semiconductor structure 200A.

FIG. 2C illustrates a schematic, cross-sectional view of a portion of semiconductor structure 200C. The semiconductor structure 200C is similar to the semiconductor structure 200B in FIG. 2B but the semiconductor structure 200C includes a liner layer 210 deposited over the semiconductor structure 200B via a liner deposition process. The liner layer 210 can be formed from silicon nitride (SiN) or a silicon oxynitride (SiO_(x)N_(y)), such as SON or Si₂N₂O.

An annealing process is performed on the liner layer 210 which gradually converts the liner layer 210 to oxide. The conversion rate of the liner layer 210 to oxide depends on various factors, such as an annealing temperature, a pressure of the steam, properties of the flowable dielectric layer (e.g., a material type and a thickness), properties of an annealing oxidant (e.g., a oxidant type and a concentration), and/or an annealing time. A thickness of the liner layer 210 may be altered during the annealing process. The properties of the annealing process may influence the thickness of the liner layer 210. For example, the thickness of the liner layer 210 may be increased as the annealing temperature, pressure of the steam, annealing time and/or thickness of flowable dielectric layer are increased. Further, the thickness of the liner layer 210 may be decreased as the annealing temperature, the pressure of the steam, the annealing time, and/or thickness of the flowable dielectric layer are decreased.

If the entire liner layer 210 is oxidized before the annealing process is complete, the underlying third layer 208 and second layer 206 may begin to be oxidized resulting in a diminished quality of the third layer 208 and the second layer 206. Therefore, the thickness of a liner layer 210 to be deposited is determined to provide sufficient protection against oxidation of the underlying third layer 208 and second layer 206 during subsequent processes, such as a flowable oxide deposition process and an annealing process. On the other hand, a thickness of the liner layer 210 should be thin enough to satisfy a density of a semiconductor integrated circuit.

The thickness of the liner layer 210 can be determined based on a thickness of the liner layer 210 remaining at the end of the annealing process. In one embodiment, the thickness of the liner layer 210 remaining can be zero (0) or substantially close to zero (0). In another embodiment, the thickness of the liner layer 210 remaining can be in a certain range, for example, between about 1 Å and about 30 Å, depending on a size requirement and/or performance requirements of a semiconductor integrated circuit, such as a power consumption, operating speed, or density.

In one embodiment, an initial width of the liner layer 201 may be between about 5 Å and about 100 Å, such as between about 20 Å and about 30 Å, for example, about 25 Å. It is contemplated that the liner layer 210 may be suitable for preventing oxidation of the layers 204, 206, 208 during a subsequent annealing process. Therefore, the liner layer 210 should be deposited with a thickness that provides sufficient protection against oxidation of the underlying Si-containing layer or SiGe layer during subsequent processes such as a flowable oxide deposition process and/or an annealing process. Also, the thickness of the liner layer 210 should be determined such that the thickness of the liner layer 210 remaining after the subsequent processes meets a size requirement of the semiconductor integrated circuit. In one embodiment, the thickness of the liner layer 210 can be determined based on resulting thicknesses of the liner layer 210 as described with respect to FIG. 3 below.

FIG. 2D illustrates a schematic, cross-sectional view of a portion of the substrate 202 and a semiconductor structure 200D. The semiconductor structure 200D is the semiconductor structure 200C illustrated in FIG. 2C after a dielectric material layer 212 is deposited. In one embodiment, the dielectric material layer 212 is a flowable dielectric layer. The flowable dielectric layer is formed of a dielectric material, such as a silicon oxide material. The dielectric material layer 212 can be formed using a high-density plasma CVD system, a plasma enhanced CVD system, and/or a sub-atmospheric CVD system, among other systems. Examples of CVD systems that may be adapted to form the dielectric material layer 212 include the ULTIMA HDP CVD® system and PRODUCER® ETERNA CVD® system, both available from Applied Materials, Inc., of Santa Clara, Calif. It is contemplated that other suitable CVD systems from other manufacturers may also be utilized.

FIGS. 2E and 2F illustrate schematic, cross-sectional views of a portion of semiconductor structures 200E and 200F, respectively. The semiconductor structures 200E and 200F correspond to the semiconductor structure 200D illustrated in FIG. 2D after an annealing process is performed. The annealing process is performed to densify the dielectric material layer 212 to a composition and a quality of a target layer. During the annealing process, the liner layer 210 is gradually converted to oxide. As the oxidation of the liner layer 210 occurs, the thickness and width of the liner layer 210 is decreased. In one embodiment, a portion of the liner layer 210 remains following the annealing process, as illustrated in FIG. 2E. In another embodiment, the entire liner layer 210 is oxidized, as illustrated in FIG. 2F.

In one embodiment, the annealing process includes a dry steam annealing process. The steam annealing process may be performed at a temperature of between about 200 degrees Celsius and about 600 degrees Celsius, such as between about 400 degrees Celsius and about 500 degrees Celsius. The steam annealing process may be performed for an amount of time between about 5 minutes and about 120 minutes, for example, about 100 minutes. In one embodiment, the dry annealing process may be performed for about 60 minutes.

In another embodiment, both a wet steam annealing process and the dry annealing process may be utilized. In this embodiment, the dry annealing process may be performed after the wet steam annealing process.

FIG. 3 illustrates cross-sectional views of semiconductor structures 350, 352, 354, 356, 358, and 360 with layers deposited thereon after an annealing process is performed according to an embodiment of the disclosure. The results of the annealing process performed on the semiconductor structures 350, 352, 354, 356, 358, and 360 can be used to determine a thickness of the liner layer that provides sufficient protection against oxidation of the underlying Si-containing layer or SiGe layer during a subsequent annealing processes.

The semiconductor structures 350, 352, and 354 illustrate results of an annealing process conducted at a temperature of 400 degrees Celsius, a pressure of 30 bar, a processing time of 1 hour, and wet etching rate ratio (WERR) of less than 2.5. The semiconductor structure 350 includes an SiO layer 302 and an SiGeOx layer 304 exposed to the annealing process described above. Prior to the annealing process, the SiO layer 302 has a thickness of about 2400 Å and the SiGe layer has a thickness of about 1024 Å. After the annealing process, the SiGe layer is converted to the SiGe oxidation (SiGeOx) layer 304.

The semiconductor structure 352 includes an SiO layer 306 with a thickness of about 2230 Å disposed on a silicon nitride (SiN) layer 308 with a thickness of about 100 Å. The SiN layer 308 is disposed on an SiGe layer 310 with a thickness of about 460 Å. After the annealing process, a small portion of the SiN layer 308 is oxidized. However, the SiN layer 308 substantially reduces an amount of oxidation of the SiGe layer 310 compared to the SiGeOx layer 304 of the semiconductor structure 350, such that substantially no oxidation of the SiGe layer 310 occurred.

The semiconductor structure 354 includes an SiO layer 312 with a thickness of about 2230 Å disposed on an SiN layer 314 with a thickness of about 20 Å. The SiN layer is disposed on an SiGe layer 316 with a thickness of about 460 Å. After the annealing process, a small portion of the SiN layer 314 is oxidized. However, the SiN layer 314 substantially reduces an amount of oxidation of the SiGe layer 316 compared to the SiGeOx layer 304 of the semiconductor structure 350, such that substantially no oxidation of the SiGe layer 316 occurred.

Lack of oxidation of SiGe layer 310 on the semiconductor structure 352 and lack of oxidation of the of the SiGe layer 316 on the semiconductor structure 354 indicate that a SiN layer with a thickness of about 20 Å or greater substantially reduces oxidation of an underlying SiGe layer of the semiconductor structure with a SiO layer with a thickness of about 2200 Å thickness during the annealing process described above.

The semiconductor structures 356, 358, and 340 illustrate results of an annealing process conducted at a temperature of 450 degrees Celsius, a pressure of 30 bar, a processing time of 1 hour, and WERR of less than 2.0. The semiconductor structure 356 includes an SiO layer 320 with a thickness of about 2230 Å disposed on a SiN layer 322 with a thickness of about 100 Å. The SiN layer 322 is disposed on an SiGe layer 324 with a thickness of about 479 Å. After the annealing process, a small portion of the SiN layer 322 is oxidized. However, the SiGe layer 324 remains intact with substantially no oxidation.

The semiconductor structure 358 includes an SiO layer 326 with a thickness of about of 2400 Å disposed on an SiN layer 328 with a thickness of about 30 Å. The SiN layer 328 is disposed on an SiGe layer 330 with a thickness of about 460 Å. After the annealing process, the entire SiN layer 328 is oxidized. However, the SiGe layer 330 remains substantially intact with substantially no oxidation.

The semiconductor structure 360 includes an SiO layer 332 with a thickness of about 2190 Å disposed on an SiN layer 334 with a thickness of about 20 Å. The SiN layer 334 is disposed on an SiGe layer with a thickness of about 620 Å (prior to the annealing process). After the annealing process, most of the SiN layer 334 is oxidized. Further, a portion of the SiGe layer (i.e., SiGeOx layer 336) with a thickness of about 280 Å is oxidized. A remaining portion of the SiGe layer 338 that is not oxidized has a thickness of about 340 Å.

Lack of oxidation to the SiGe layers 324 and 330 of the semiconductor structures 356 and 358, respectively, and the small SiGeOx layer 336 with respect to the SiGeOx layer 304, indicates that an SiN layer with a thickness of about 30 Å or greater substantially reduces oxidation of an underlying SiGe layer of the semiconductor structure which includes an SiO layer with a thickness of about 2400 Å during the annealing process described above.

FIG. 4 is a schematic top view of a processing system 480 that can be used to perform the fabrication process illustrated in FIG. 1 according to an embodiment of the present disclosure. The cluster system 480 is a modular system comprising multiple chambers (e.g., process chambers 490A-490D, service chambers 491A-491B, or the like) which perform various functions, including: substrate center-finding and orientation, degassing, annealing, deposition, etching, and the like.

The process chambers 490A-490D of the cluster system 480 include a deposition chamber, an etch chamber, a plasma chamber, and an annealing chamber, configured to perform at least portions of the fabrication process 100, and may further include chambers such as an ion implantation chamber and the like.

The chambers 490A-490D include a processing chamber comprising a chamber wall forming a process volume therein, a substrate support for supporting a substrate within the process volume, a pressure regulator for regulating the pressure in the process volume, a gas inlet for providing gas tothe process volume, and a gas outlet for exhausting gas from the process volume.

The plasma chamber includes at least one electrode to provide power to a plasma chamber enclosure for generating and sustaining a plasma therein. The plasma chamber also includes at least one RF power source electrically connected to the at least one electrode.

The etching chamber includes an etching gas source to feed an etching gas into a processing chamber. The deposition chamber includes precursor gas sources to introduce reactive gases into a processing chamber. The annealing chamber includes an annealing gas source to introduce an annealing gas into a processing chamber. An ion implantation chamber comprises an arc chamber, filaments positioned within the arc chamber, and a repeller structure positioned between the filaments and the arc chamber.

The duster system 480 for practicing embodiments of the present disclosure includes a first deposition chamber configured to form a semiconductor structure on a substrate where the semiconductor structure includes a silicon (Si) containing layer or a silicon germanium (SiGe) layer. The cluster system 480 also includes an etch chamber configured to etch a patterned semiconductor structure and a second deposition chamber configured to perform a liner deposition process to form a liner layer over the semiconductor structure. A third deposition chamber of the cluster system 480 is configured to perform a flowable layer deposition process to form a flowable layer over the liner layer. An annealing chamber of the cluster system 480 is configured to perform an annealing process by exposing the flowable layer to high pressure steam. The cluster system 480 further includes a lithograph device to pattern the semiconductor structure using extreme ultraviolet light.

The multiple chambers 490A-490D of the cluster system 480 are mounted to a central vacuum transfer chamber 488 which houses a robot 489 adapted to transfer substrates between the chambers 490A-490D. The vacuum transfer chamber 488 is maintained at a vacuum condition and provides an intermediate stage for transferring substrates from one chamber to another, and/or to a load lock chamber 484 positioned at a front end of the cluster system 480. A front-end environment 483 is positioned in selective communication with the load lock chambers 484. A pod loader 485 disposed in the front-end environment 483 is capable of linear and rotational movement (arrows 482) to transfer cassettes of substrates between the load lock chambers 484 and a plurality of pods 487 which are mounted on the front-end environment 483.

The cluster system 480 also includes a controller 481 programmed to carry out the various processing methods performed in the cluster system 880. For example, the controller 481 may be configured to control a flow of various precursor and process gases from gas sources and control processing parameters associated with material deposition or etching processes. The controller 481 includes a programmable central processing unit (CPU) 479 that is operable with a memory 477, and a mass storage device, an input control unit, and a display unit (not shown), such as power supplies, clocks, cache, input/output (I/O) circuits, and the like, coupled to the various components of the cluster system 480 to facilitate control of the substrate processing. The controller 481 also includes hardware for monitoring substrate processing through sensors in the cluster system 480. Other sensors that measure system parameters such as substrate temperature, chamber atmosphere pressure, and the like, may also provide information to the controller 481.

To facilitate control of the cluster system 480 described above, the CPU 479 may be one of any form of general purpose computer processor that can be used in an industrial setting, such as a programmable logic controller (PLC), for controlling various chambers and sub-processors. The memory 477 is coupled to the CPU 479 and the memory 477 is non-transitory and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. Support circuits 475 are coupled to the CPU 479 for supporting the processor in a conventional manner. Deposition, etching, annealing, and other processes are generally stored in the memory 477, typically as a software routine. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 479.

The memory 477 is in the form of computer-readable storage media that contains instructions, that when executed by the CPU 479, facilitates the operation of the cluster system 480. The instructions in the memory 477 are in the form of a program product such as a program that implements the methods of the present disclosure. The program code may conform to any one of a number of different programming languages. In one example, the disclosure may be implemented as a program product stored on computer-readable storage media for use with a computer system. The program(s) of the program product include functions of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., a disk storage or a hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.

While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. 

1. A method for processing a substrate, comprising: forming a semiconductor structure on the substrate, wherein the semiconductor structure includes a silicon (Si) containing layer or a silicon germanium (SiGe) layer; performing a liner deposition process to form a liner layer over the semiconductor structure; performing a flowable layer deposition process to deposit a flowable dielectric layer over the liner layer; and performing an annealing process by exposing a surface of the flowable dielectric layer to high pressure steam, wherein at least a portion of the liner layer is gradually reduced by oxidation during the annealing process.
 2. The method of claim 1, wherein a thickness of the liner layer is determined based on a thickness of the liner layer remaining after the annealing process is completed.
 3. The method of claim 1, wherein a thickness of the liner layer is determined based on at least one of an annealing time, an annealing temperature, and a thickness of the flowable dielectric layer, and wherein the thickness of the liner layer is substantially zero.
 4. The method of claim 1, wherein the liner layer is formed of silicon nitride or silicon oxynitride.
 5. The method of claim 1, wherein the flowable layer deposition process comprises reacting a silicon-containing precursor and an oxygen-based radical precursor at a temperature of between 0 degree Celsius and about 100 degrees Celsius at a chamber pressure of between about 1 Torr and about 10 Torr, wherein the silicon-containing precursor includes trisilylamine.
 6. The method of claim 1, wherein the annealing process comprises exposing the flowable dielectric layer to high pressure steam in an annealing chamber at a pressure from about 1 bar to about 60 bar at a temperature between about 200 degrees Celsius to about 600 degrees Celsius during a time of between about 5 minutes and about 120 minutes.
 7. The method of claim 1, wherein the annealing process is a high pressure, dry steam annealing process.
 8. A method for processing a substrate, comprising: forming a semiconductor structure on the substrate, wherein the semiconductor structure includes a silicon (Si) containing layer or a silicon germanium (SiGe) layer; performing a liner deposition process to form a liner layer over the semiconductor structure; performing a flowable layer deposition process to deposit a flowable dielectric layer over the liner layer; and performing an annealing process by exposing a surface of the flowable dielectric layer to high pressure steam, wherein the liner layer prevents oxidation of the Si containing layer or SiGe layer during the annealing process, at least a portion of the liner layer is gradually reduced by oxidation during the annealing process.
 9. The method of claim 8, wherein a thickness of the liner layer is determined based on a thickness of the liner layer remaining after the annealing process is completed.
 10. The method of claim 8, wherein a thickness of the liner layer is determined based on at least one of an annealing time, an annealing temperature, and a thickness of the flowable dielectric layer.
 11. The method of claim 8, wherein a thickness of the liner layer is determined such that a thickness of the liner layer remaining after the annealing process equals to substantially zero, and wherein the liner layer is formed of silicon nitride or silicon oxynitride.
 12. The method of claim 8, wherein the flowable layer deposition process comprises reacting a silicon-containing precursor and an oxygen-based radical precursor at a temperature of between about 0 degree Celsius and about 100 degrees Celsius at a chamber pressure of between about 1 Torr and about 10 Torr, wherein the silicon-containing precursor includes trisilylamine.
 13. The method of claim 8, wherein the annealing process comprises exposing the flowable dielectric layer to high pressure steam in an annealing chamber at a pressure from about 1 bar to about 60 bar at a temperature between about 200 degrees Celsius to about 600 degrees Celsius during a time of between about 5 minutes and about 120 minutes.
 14. The method of claim 8, wherein the annealing process is a high pressure, dry steam annealing process.
 15. A cluster system configured to process a substrate, comprising: a central vacuum transfer chamber; a first deposition chamber coupled to the central vacuum transfer chamber and configured to process the substrate; a second deposition chamber coupled to the central vacuum transfer chamber and configured to process the substrate; a third deposition chamber coupled to the central vacuum transfer chamber and configured to process the substrate; an annealing chamber coupled to the central vacuum transfer chamber and configured to process the substrate; a robot disposed in the central vacuum transfer chamber, the robot configured to transfer the substrate between each of the first deposition chamber, the second deposition chamber, the third deposition chamber, the annealing chamber, and the central vacuum transfer chamber; and a controller electrically coupled to the robot, the first deposition chamber, the second deposition chamber, the third deposition chamber, the annealing chamber, and the central vacuum transfer chamber, the controller configured to cause the cluster system to: deposit a silicon (Si) containing layer or a silicon germanium (SiGe) layer on the substrate in the first deposition chamber; transfer the substrate from the first deposition chamber to the second deposition chamber via the robot; deposit a liner layer over the silicon (Si) containing layer or the silicon germanium (SiGe) layer in the second deposition chamber; transfer the substrate from the second deposition chamber to the third deposition chamber via the robot; form a flowable dielectric layer over the liner layer in the third deposition chamber; transfer the substrate from the third deposition chamber to the annealing chamber via the robot; and perform an annealing process in the annealing chamber by exposing the flowable dielectric layer to high pressure steam in the annealing chamber.
 16. The cluster system of claim 15, wherein the second deposition chamber is configured to deposit the liner layer in a thickness such that a minimum portion of the liner layer remains until end of the annealing process.
 17. The cluster system of claim 15, wherein the second deposition chamber is configured to deposit the liner layer having a thickness, wherein the thickness of the liner layer is determined based on a thickness of a remaining liner layer at end of the annealing process.
 18. The cluster system of claim 15, wherein the second deposition chamber is configured to deposit the liner layer having a thickness, wherein the thickness of the liner layer is further determined based on at least one of an annealing time, an annealing temperature, and a thickness of the flowable dielectric layer.
 19. The cluster system of claim 15, wherein the second deposition chamber is configured to deposit the liner layer having a thickness, wherein the thickness of the liner layer is determined such that a thickness of a remaining liner layer at end of annealing process equals to substantially zero.
 20. The cluster system of claim 15, wherein the liner layer is formed of silicon nitride or silicon oxynitride. 